The present invention relates to a method for designing a semiconductor integrated circuit (LSI), and more particularly, to a design method, a design device, and a logic design program that are employed during the logic design stage for an LSI.
When designing an LSI, after performing logic design, physical design (layout design) is performed in a downstream process. During layout design, data obtained during the logic design is used to generate layout data. The layout data is subsequently checked. When the layout data does not satisfy the design conditions, layout design or logic design is performed again. That is, redesign is performed. Redesign (returning to an earlier point in the design flow) prolongs the design time. It is desired that the number of times of redesign is performed be reduced so that the LSI design is performed efficiently.
In the prior art, during logic design, the designing of a register transfer level (RTL) is performed based on the design specification of an LSI. Afterwards, logic synthesizing is performed based on the RTL design data to generate logic circuit data for a gate level, that is, to generate a so-called net list. When generating the net list, a target design value is provided with a margin based on data obtained during previous designing. The margin, which is determined through experience, absorbs the difference between the logic design and the layout design, or deviation from a target value, to reduce the number of times redesign is performed after layout design.